Architenture

• The XMOS architecture combines a number of processing cores (called XCores) each with its own memory and I/O system, on a single chip. The processing cores are general-purpose in the sense that they can execute languages such as C; they also have direct support for concurrent processing (multi-threading), communication and I/O.
• A high-performance switch supports communication between the processors, and inter-chip Links are provided so that systems can easily be constructed from multiple chips. Any thread can communicate with any other thread in the system using single-cycle communication instructions. The system switches can efficiently route short packets or streamed data.
• The XMOS architecture makes it practical to use software to perform many functions that traditionally have been implemented in hardware, for example interfaces and I/O controllers. Both input and output operations can be timed to a local clock or an externally provided clock. The architecture is both multi-threaded and event-driven. Threads can be used to define independent tasks; the event mechanism enables fast and controlled responses to a multitude of signals.
• The architecture is designed to support any programming language, such as C and C++. The full benefits of the instruction set may require extensions to standard languages, libraries, or the use of assembly language. We have designed XC, a version of C that supports I/O, multi-core and precision timing.

XCORE

An XCore processor runs multiple real-time threads simultaneously. Each thread has access to a set of general purpose registers, gets a guaranteed share of the processing power, and executes a program using common RISC-style instructions. Each thread can execute simple computational code, DSP code, control software (taking logic decisions, or executing a state machine) or handle I/O operations.

Threads share a memory and can use this shared memory to exchange data, or they can use channels to exchange data and synchronise. If shared memory is used, then threads can use single-cycle lock instructions in order to co-ordinate access. If channels are used for communication, then single cycle instructions can transfer a word of data.

I/O pins can be set and sampled in a single instruction. Simple input and output instructions transfer data to or from I/O ports. More complex use allows data to be serialised and deserialised, enabling the processor to keep up with high speed data streams. The ports can timestamp data and synchronise transfers with an external clock.

The XCore is event driven and threads waiting for events do not consume any processing resources. An event can be the completion of a communication or I/O operation, the release of a lock or a timer reaching a programmed time. Threads can wait for any one of a set of events. The first event will cause the thread to start in a single instruction.